Known gate spacer fabrication methods are described below. First, an STI (shallow trench isolation) structure and a well are formed in a semiconductor substrate. Then, a gate oxide layer and a gate polysilicon layer are deposited and patterned to form a gate. Dopants of low concentration are then implanted by using the gate as a mask to form an LDD (lightly doped drain) region. A TEOS (tetra-ethoxysilane) layer and a nitride layer are deposited and etched through a dry etch process by using CH3F/CH4 gases to form gate spacers. Finally, source and drain regions are formed by implanting the ions of high concentration.
However, if CxFy gases are used for the dry etch, an etch selectivity of more than 3 between the oxide layer and the nitride layer is difficult to achieve. Thus, while the nitride layer for spacers is selectively etched, the oxide layer on a silicon substrate is unintentionally damaged, which results in exposure of the surface of a device active region to plasma. If the surface of the silicon substrate is exposed to plasma, the dopants of a well region are decreased and a photoresist is coated directly on the silicon substrate, which causes its contamination by organic materials. Furthermore, the effectiveness of the ion implantation to form the source and drain regions can be reduced due to the contamination by organic materials.